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pr e l i m i n a r y dcc-dd041157-3 1/37 256mb ddr sdram ordering information em 42 am 16 8 4 r t a ?75 l eorex memory edo/fpm : 40 d-rambus : 41 ddrsdram : 42 ddrsgram : 43 sgram : 46 sdram : 48 power s : standard l : low power package f : pb-free g : green density 32m : 32 mega bits 4m : 4 mega bits 16m : 16 mega bits 2m : 2 mega bits 8m : 8 mega bits 1m : 1 mega bit refresh 1 : 1k 8 : 8k 2 : 2k 6 :16k 4 : 4k bank 2 : 2bank 6 : 16bank 4 : 4bank 3 : 32bank 8 : 8bank revision a : 1st b : 2nd c :3rd d :4 th g : for vga version only interface v : 3.3v r : 2.5v package min cycle time ( max freq.) -5 : 5ns ( 200mhz ) -6 : 6ns ( 167mhz ) -7 : 7ns ( 143mhz ) -75 : 7.5ns ( 133mhz ) -8 : 8ns ( 125mhz ) -10 : 10ns ( 100mhz ) c : csp b : ubga t :tsop q :tqfp p : pqfp ( qfp ) l : lqfp organization 4 : x4 16 : x16 8 : x8 18 : x18 9 : x9 32 : x32
pr e l i m i n a r y dcc-dd041157-3 2/37 256mb ddr sdram description the em42am16 8 4rta is a high speed synchronous graphic ram fabricated with ultra high performance cmos process containing 268,435 ,456 bits which organized as 4 banks, each banks has 8,192 rows x 512 columns x 16 bits. the 256mb ddr sdram uses a double data rate architecture to accomplish high-speed operation. the data path internally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. it means the doubled data bandwidth can be achieved at the i /o pins. * eorex reserves the right to change pr oducts or specificat ion without notice. 256mb( 4banks ) double data rate sdram 200 mhz 166 mhz 133 mhz part number max. frequency i/o interface em42am16 8 4rta-5 sstl-2 em42am16 8 4rta-6 sstl-2 em42am16 8 4rta-75 sstl-2 ordering information package 66 pins, tsopii 66 pins, tsopii 66 pins, tsopii em42am16 8 4rta ( 16mx16 ) features ? internal double-data-rate architecture with 2 accesses per clock cycle ? 4 banks operation ? bi-directional, intermittent data strobe (dqs) ? all inputs except data and dm are sampled at the positive edge of the system clock. ? data mask (dm) for write data ? auto & self refresh supported ? 8k refresh cycle / 64ms ? burst length of 2,4,8 ? sequential & interleaved burst type available ? 2,2.5, 3 clock read latency ? auto precharge option for each burst accesses ? dqs edge-aligned with data for read cycles ? dqs center-aligned with data for write cycles ? dll aligns dq & dqs transitions with clk transition ? 2.5v+/- 0.2v vdd ? 2.5v sstl-2 compatible i/o
pr e l i m i n a r y dcc-dd041157-3 3/37 256mb ddr sdram 66pin tsop-ii (400mil x 875 mil) (0.65mm pin pitch) pin assignment ( top view ) v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v ddq ldqs nc v dd /qfc/nc ldm /we /cas /ras /cs nc ba0 ba1 ap/a10 a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ssq udqs nc v ref v ss udm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
pr e l i m i n a r y dcc-dd041157-3 4/37 256mb ddr sdram pin name pin function clk, /clk system clock clock input active on the positive rising edge except for dq and dm are active on bot h edge of the dqs. clock and /clock are differential clock inputs. /cs chip select /cs enables the command decoder when ?l? and disabled the command decoder when ?h?. the new commands are over- looked when the command decoder is disabled but previous operation will still continue. cke clock enable activates the clk when ?h? and deactivates when ?l?. when deactivate the clock, cke low signifies the power down or self refresh mode. a0 ~ a12 address row address (a0 to a12) and column address (ca0 to ca8) are multiplexed on the same pins. ca10 defines auto precharge at column address . /ras row address strobe latches row addresses on t he positive rising edge of the clk with /ras ?l?. enables row access & pre-charge. /cas column address strobe latches column addresses on the positive rising edge of the clk with /cas low. enables column access. /we write enable latches column addresses on the positive rising edge of the clk with /cas low. enables column access. ldqs,udqs data input/output data inputs and outputs ar e synchronized with both edge of dqs. pin descriptions ( simplified ) ba0, ba1 bank address selects which bank is to be active. dq0 ~ 15 data input/output data inputs and outputs are multiplexed on the same pin. v dd /v ss power supply/ground v dd and v ss are power supply pins for internal circuits. nc/ rfu no connection / reserved for future use this pin is recommended to be left no connection on the device. v ddq /v ssq power supply/ground v ddq and v ssq are power supply pins for the output buffers. ldm,udm data input/output mask dm controls data inputs. ldm corresponds to the data on dq0-dq7. udm corresponds to the data on dq8-dq15 /qfc data output fet control : emrs option output during every read and write access. it can be used to control isolation switches on modules. v ref input sstl-2 reference voltage for input buffer.
pr e l i m i n a r y dcc-dd041157-3 5/37 256mb ddr sdram burst counter row add. buffer col. add. buffer col. decoder s/a & i/o gating block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 timing register row decoder memory array address register mode register set (extended m-r-s) auto/self refresh counter col. add. counter data in data out dqi clk /clk cke /cs /ras /cas /we dm dqs write dqm control dm
pr e l i m i n a r y dcc-dd041157-3 6/37 256mb ddr sdram c k e l c k e h idle row active power down cbr (auto) refresh self refresh mode register set write writea read reada precharge power on simplified state diagram s e l f s e l f e x i t re f m rs c k e l c k e h a ct b s t r e a d r e a d w r i t e r e a d w r i t e w i t h r e a d w i t h p r e / p a l l p re p re w r i t e m a n u a l i n p u t a u t o m a t i c s e q u e n c e w r i t e a r e a d a b u r s t e n d power down
pr e l i m i n a r y dcc-dd041157-3 7/37 256mb ddr sdram absolute maximum ratings symbol item rating units v in , v out input, output voltage -0.3 ~ 3.6 v v dd , v ddq power supply voltage -0.3 ~ 3.6 v t op operating temperature 0 ~ 70 c t stg storage temperature -55 ~ 150 c p d power dissipation 1 w i os short circuit current 50 ma recommended dc operation condition s ( ta = 0 ~ 70 c ) note : caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. ex posure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter v dd power supply voltage v ddq power supply voltage (for i/o buffer) min. 2.3 2.3 units v v typical 2.5 2.5 max. 2.7 2.7 v ref i/o logic high voltage v tt i/o termination voltage 1.15 v ref -0.04 v v 1.25 - 1.35 v ref +0.04 capacitance ( vcc =2.5v, f = 1mhz, ta = 25 c ) symbol parameter min. units c clk clock capacitance ( clk, /clk ) 2.5 pf c i input capacitance for cke, address, /cs, /ras, /cas, /we 2.5 pf max. 4.0 4.5 c o dm , data & dqs input/output capacitance 4.0 pf 6.5 v ih input logic high voltage v il input logic low voltage v ref +0.18 -0.3 v v - - v ddq +0.3 v ref -0.18
pr e l i m i n a r y dcc-dd041157-3 8/37 256mb ddr sdram recommended dc operating conditions ( ta = 0 ~ 70 c ) note : 1. idd1 and idd4 depends on output loading and cycle rates. specified values are obtained with the output open. 2. min. of t rfc ( auto refresh row cycle times ) is shown at ac characteristics. precharge standby current in power down mode operating current parameter test condition burst length = 2, t rc t rc (min), iol = 0 ma, one bank active cke v il (max.), t ck = min symbol i dd1 i dd2p speed 110 -5 4.5 ma units ma notes 1 95 -6 85 -75 precharge standby current in non-power down mode cke v ih (min.), t ck = min, /cs v ih (min.) input signals are changed one time during 2clks i dd2n 40 ma active standby current in power down mode active standby current in non-power down mode ma cke v ih (min), t ck = min, / cs v ih (min) input signals are changed one time during 2clks i dd3n 45 ma cke v il (max.), t ck = min i dd3p 15 refresh current ma 2 t rc t rfc (min.), all banks active i dd5 self refresh current cke 0.2v i dd6 2 self refresh current cke 0.2v i dd6 2 ma self refresh current cke 0.2v i dd6 2 160 operating current ( burst mode ) t ck t ck (min.), i ol = 0 ma all banks active i dd4 read write 110 100 ma 1
pr e l i m i n a r y dcc-dd041157-3 9/37 256mb ddr sdram parameter input leakage current output leakage current high level output voltage low level output voltage symbol i li i lo v oh v ol unit ua ua v v min. -5 -5 v tt + 0.76 - v tt - 0.76 max. 5 5 - recommended dc operating conditions ( continued ) i oh=-15.2ma note 1 2 i oh=-15.2ma note : 1. v in = 0 to 3.6v all other pins are not tested under v in = 0v. 2. dout is disabled, v in = 0 to 2.7v.
pr e l i m i n a r y dcc-dd041157-3 10/37 256mb ddr sdram operating ac characteristics ( v dd = 2.5v +/- 0.2 v, ta = 0 ~ 70 c ) parameter symbol units -6 -5 -75 min. max. min. max. min. max. dq output access from clk, /clk t dqck dqs output access from clk, /clk t dqsck ck low / high level width t cl ,t ch ns -0.7 +0.7 -0. 5 +0. 5 -0.75 +0.75 t ck 0.45 0.55 0.45 0.55 0.45 0.55 ns -0.6 +0.6 -0. 5 +0. 5 -0.75 +0.75 ns 6 12 7.5 12 7.5 12 ns 6 12 6 12 7.5 12 clock cycle time t ck cl=2 cl=2.5 dq and dm hold / setup time t dh ,t ds data out high / low impedance time from clk, /clk t hz , t lz ns -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 dqs-dq skew for associated dq signal t dqsq ns 0.45 0.4 ns 0.45 0.4 0.5 ns 1.75 1.75 1.75 write command to first latching dqs transition t dqss t ck 0.75 1.25 0.7 1.25 0.75 1.25 active to read or write delay t rcd precharge command period t rp active bank a to b command period t rrd dqs input valid window t dsl , t dsh mode register set command cycle time t mrd write preamble setup time t wpres write postamble t wpst t ck 0.35 0.35 0.35 t ck 2 2 2 ns 0 0 0 t ck 0.4 0.6 0.4 0.6 0.4 0.6 auto refresh row cycle time t rfc address /control input hold / setup time t ih ,t is read preamble t rpre read postamble t rpst active to precharge command period t ras active to active command period t rc ns 0.8 0.7 1.0 t ck 0.9 1.1 0.9 1.1 0.9 1.1 t ck 0.4 0.6 0.4 0.6 0.4 0.6 ns 42 70k 40 70k 45 70k column address to column address delay t ccd ns ns 72 60 70 55 75 65 ns ns ns t ck 18 18 12 1 15 15 10 1 20 20 15 1 dq and dm input pulse width for each input t dipw 0.5
pr e l i m i n a r y dcc-dd041157-3 11/37 256mb ddr sdram operating ac character istics ( continued ) ( v dd = 2.5v +/- 0.2 v, ta = 0 ~ 70 c ) last data in to read command t cdlr t ck t ck 0 0 0 t ck 2 2 2 exit self refresh to non-read command exit self refresh to read command ns 75 ns 200 2.5t ck -t dqss 2.5t ck -t dqss 2.5t ck -t dqss parameter symbol units -8 -75 -10 min. max. min. max. min. max. average periodic refresh interval us 15.6 15.6 15.6 t ck 1.1 1.1 0.9 1.1 /qfc postamble during reads t ck 0.6 0.6 0.4 0.6 /qfc output access time from ck/ /ck t qck ns 0 0 0 75 200 0.9 0.4 t ck 0.4 0.6 0.6 0.4 0.6 0.4 last data in to precharge command t dpl last data in to write command t cdlw /qfc preamble during reads t qpst t xsnr t xsrd t refi t qpre 75 200 0.9 0.4 t qoh /qfc output hold time
pr e l i m i n a r y dcc-dd041157-3 12/37 256mb ddr sdram truth table 1. command truth table command symbol cke ignore command desl no operation nop h h x n-1 n /cs h l x /ras x h /cas x h /we x h ba0, ba1 x x a10 x x a12 ~a0 x x burst stop bsth read read h h x l l x h h h l l h x v x l x v read with auto pre-charge reada write writ h h x l l x h h l l h l v v h l v v write with auto pre-charge writa bank activate act h h x l l x h l l h l h v v h v v v pre-charge select bank pre h l x l h l v l x pre-charge all banks pall mode register set mrs h h x l l x l l h l l l x l h l x v note : h = high level, l = low level, x = high or low level (don't care), v = valid data input 2. cke truth table command symbol cke n-1 n /cs /ras /cas /we addr. command remark h = high level, l = low level, x = high or low level ( don't care ) idle ref h l h l l h x idle self self refresh h l l l l h l h l h h h x x idle power down h l l x x h x x x x x x x x cbr refresh command self refresh entry self refresh exit power down entry power down exit l h h x x x x
pr e l i m i n a r y dcc-dd041157-3 13/37 256mb ddr sdram 3. operative command table x x desel nop addr. command x x x ba/ca/a10 ba/ra ba/a10 desel nop term read/writ/bw act pre/prea x refa x term ba/ca/a10 read/reada ba/ca/a10 write/writea current state idle l l h h l l h l /cs /r /c /w h x x x l h h h l h h l l h l x l l l h l l l l x h row active h l x h x h l l h h h l h l l l h l op-code, mode-add nop nop action nop nop nop illegal bank active , latch ra nop auto refresh nop begin read, latch ca, determine auto-precharge begin write, latch ca, determine auto-precharge notes 1 3 4 mrs mode register 5 ba/a10 pre/prea l h l l h l l l l l l l op-code, mode-add precharge / precharge all x refa illegal mrs illegal x x x desel nop term ba/ca/a10 read/reada ba/a10 x pre/prea read x h l h l x h x h l h h h l h l l l h l l h l l h l l l l l l l op-code, mode-add nop ( continue burst to end ) nop ( continue burst to end ) terminal burst terminal burst. latch ca,begin new read, determine auto-precharge terminate burst, precharge illegal mrs illegal refa remark: h =high level, l=low level, x=high or low level ( don?t care ), ap= auto precharge ba/ra act h l l h illegal 1 ba/ra act h l l h illegal 1
pr e l i m i n a r y dcc-dd041157-3 14/37 256mb ddr sdram addr. command action x x x desel nop term nop ( continue burst to end ) nop ( continue burst to end ) illegal ba/ca/a10 read/reada terminate burst with dm=?h?, latch ca , begin read,determine auto-precharge ba/ca/a10 write/writea terminate burst , latch ca ,begin new write, determine auto-precharge current state write /cs /r /c /w h x x x l h h h l h h l l h l h l h l l notes 5 5 2 2 op-code, mode-add ba/ra ba/a10 x act pre/prea refa illegal terminate burst with dm=?h?, precharge illegal l l l l l l h h l l h l l l l h mrs illegal 5 1 x x desel nop nop ( continue burst to end ) nop ( continue burst to end ) ba/ca/a10 term illegal ba/a10 x x act pre/prea refa illegal illegal illegal op-code, mode-add ba/ra read/write illegal x x desel nop nop (continue burst to end ) nop (continue burst to end ) x term illegal ba/ra ba/a10 x act pre/prea refa illegal illegal illegal op-code, mode-add ba/ca/a10 read/write x h read with auto- precharge h l x h x h l l h h h l h l l h l l h l l l l l l l x l h l x h write with auto- precharge h l x h x h l l h h h l h l l h l l h l l l l l l l x l h l illegal 1 1 mrs illegal 1 1 mrs illegal 1 1 remark: h =high level, l=low level, x=high or low level ( don?t care ), ap= auto precharge
pr e l i m i n a r y dcc-dd041157-3 15/37 256mb ddr sdram x x desel nop nop ( idle after t rp ) nop ( idle after t rp ) x term nop ba/ra ba/a10 x act pre/prea refa illegal nop( idle after t rp ) illegal op-code, mode-add ba/ca/a10 read/write illegal x x desel nop nop (row active after t rcd ) nop (row active after t rcd ) x term nop ba/ra ba/a10 x act pre/prea refa illegal illegal illegal op-code, mode-add ba/ca/a10 read/write illegal x h precharging h l x h x h l l h h h l h l l h l l h l l l l l l l x l h l x h row activating h l x h x h l l h h h l h l l h l l h l l l l l l l x l h l 1 3 mrs illegal 1 1 mrs illegal 1 1 remark: h =high level, l=low level, x=high or low level ( don?t care ), ap= auto precharge addr. command action current state /cs /r /c /w write recovering x x desel nop nop ( ldle after t rp ) nop ( ldle after t rp ) x term nop ba/ra ba/a10 x act pre/prea refa illegal illegal illegal op-code, mode-add ba/ca/a10 read/write illegal x h refreshing h l x h x h l l h h h l h l l h l l h l l l l l l l x l h l mrs illegal notes 1 ba/a10 x pre/prea refa illegal illegal l l l l h x x desel nop nop nop x term nop ba/ca/a10 read illegal ba/ca/a10 write/writea x h h l x h x h l l h h h l h l l l h l new write, determine ap ba/ra act illegal l h l h l h l l l l l 1 1 op-code, mode-add mrs illegal note 1. illegal to bank in specified state: function may be legal in the bank indicated by bans address (ba), depending on the state of the bank. 2. must satisfy bus contention, bus turn around, and/or write recovery requirements. 3. nop to bank precharging or in idle sate. may precharge bank indicated by ba. 4. illegal of any bank is not idle.
pr e l i m i n a r y dcc-dd041157-3 16/37 256mb ddr sdram 4. command truth table for cke notes 1. after cke?s low to high transition to exist self refresh mode. and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command. 2. cke low to high transition is asynchronous as if restarts internal clock. 3. power down and self refresh can be entered only from the idle state of all blanks. remark : h = high level, l = low level, x = high or low level (don't care) addr. action notes x x x x x x x invalid exist self-refresh exist self-refresh illegal illegal illegal nop ( maintain self-refresh ) 1 1 x x x x x refer to function true table enter power down enter power down illegal illegal 3 3 ra x op code op-code x row active / bank active enter self-refresh mode register access special mode register access refer to current state 3 x refer to command truth table x x x x x x x invalid exist power down exist power down illegal illegal illegal nop ( maintain power down ) 2 2 current state /cs /r /c n-1 n cke /w self refreshing x h x x x x l l h h h h l h l l x l x x x h l l l l l l x h h h h h l x x h l x x x all banks idle x h x x x x l h h l h h l h l h h h h h h l l l l x x h l x l l h l l l h h l l l l l l l l x x x h h l l l x h h l l x any state other than listed above x x x x h h both bank precharge power down x h x x x x l l h h h h l h l l x l x x x h l l l l l l x h h h h h l x x h l x x x
pr e l i m i n a r y dcc-dd041157-3 17/37 256mb ddr sdram mode register definition mode register set the mode register stores the data for controlling the various operating modes of ddr sdram which contains addressing mode, burst length, /cas latency, test mode, dll reset and various vendor?s specific opinions. the defaults values of the register is not defined, so the mode register must be written after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on /cs, /ras, /cas, /we and ba0 ( the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register. ) the state of the address pins a0-a12 in the same cycle as /cs, /ras, /cas, /we and ba0 going low is written in the mode register. two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0-a2, addressing mode uses a3, /cas latency ( read latency from column address ) uses a4-a6. a7 is used for test mode. a8 is used for ddr reset. a7 must be set to low for normal mrs operation. mrs cycle t rp 01 2345 67 8 clk, /clk command nop precharge all banks nop mrs any command nop nop nop 2clk nop
pr e l i m i n a r y dcc-dd041157-3 18/37 256mb ddr sdram a8 a7 a6 a5 a4 a3 a2 a1 a0 tm cas latency bt burst length a9 a10 rfu ba0 ba1 address input for mode register set a2 a1 a0 sequential burst length interleave 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 1 interleave 0 sequential a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 1 reserved a7 0 1 operation mode normal test a8 0 1 dll reset no yes ba0 0 1 an ? a0 mrs cycle emrs 1 1 0 2.5 a12/11
pr e l i m i n a r y dcc-dd041157-3 19/37 256mb ddr sdram burst type ( a3 ) a2 a1 a0 interleave addressing burst length x x 0 0 1 2 x x 1 1 0 x 0 0 0 1 2 3 4 x 0 1 1 0 3 2 x 1 0 2 3 0 1 x 1 1 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 8 0 0 1 1 0 3 2 5 4 7 6 sequential addressing 0 1 1 0 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 0 1 0 2 3 0 1 6 7 4 5 0 1 1 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 1 0 1 5 4 7 6 1 0 3 2 1 1 0 6 7 4 5 2 3 0 1 1 1 1 7 6 5 4 3 2 1 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 * page length is a function of i/o organization and column addressing dll enable / disable the dll must be enabled for normal operation. dll enable is requir ed during power-up initialization and upon returning to normal o peration after having di sable the dll for the purpose of debug or evaluati on ( upon existing self refres h mode, the dl l is enable automatically. ) any time the dll is enab led, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength got all outputs is specified to be sstl-2, class ii. some vendors might also support a weak drive streng th option, intended for lighter load and/or point to point environments.
pr e l i m i n a r y dcc-dd041157-3 20/37 256mb ddr sdram extended mode regi ster set ( emrs ) the extended mode register stores the data enabling or disabling d ll. the value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling dll. the extended mode regist er is written by asserting low on /cs, /ras, /cas, /we and high on ba0 ( the ddr sdram should be in all bank precharge with cke already prior to writing into the extended mode register. ) the state of address pins a0-a10 and ba1 in the same cycle as /cs, /ras, /cas, and /we going low is written in the extended mo de register. the mode register contents can be changed using the same command and clo ck cycle requirements during operation as long as all banks are in the id le state. a0 is used for dll e nable or disable. high on ba0 is used for emrs. all the other address pins except a0 and ba0 must be set to low for proper emrs operation. a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu : must be set as 0 0 output driver impedance control normal 1 weak a0 0 1 dll enable enable disable a9 a10 ba0 0 1 an ? a0 mrs cycle emrs /qfc d.i.c dll rfu ba0 ba1 1 qfc control a12/11 disable 0 enable 1
pr e l i m i n a r y dcc-dd041157-3 21/37 256mb ddr sdram /qfc function /qfc definition when drive low in reads coincident wit h the start of dqs, this dram output signal says that one cycle later there will be the first valid dqs output and returned on hi-z after this finishing a burst operation. it is also driven low shortly after a write command is received and returned to hi-z shortly after the last data strobe transition is received. whenever the device is in standby, the signal is hi-z. dqs is in tended to enable an external data switch. qfc can be enabled or di sabled through emrs control. /qfc timing or read operation qfc on reads is enabled coincident with the start of dqs preamble, and disabled coincident with the end of dqs postamble clk, /clk command dqs dqs /qfc read 012345678 dout0 dout1 t qpst t qpre hi-z cl=2. bl=2
pr e l i m i n a r y dcc-dd041157-3 22/37 256mb ddr sdram /qfc timing on write op eration with tdqssmax /qfc on writes is enabled as soon as pos sible after the clock edge of write command and disabled as soon as possi ble after the last dqs-in low going edge. 012345678 clk, /clk command dqs@tdqsmax dqs@tdqssmax /qfc write dout0 dout1 t qoh hi-z bl=2 t qck
pr e l i m i n a r y dcc-dd041157-3 23/37 256mb ddr sdram /qfc timing on write op eration with tdqssmin /qfc on writes is enabled as soon as pos sible after the clock edge of write command and disabled as soon as possi ble after the last dqs-in low going edge. 012345678 clk, /clk command dqs@tdqsmin dqs@tdqssmin /qfc write dout0 dout1 t qoh bl=2 hi-z t qck
pr e l i m i n a r y dcc-dd041157-3 24/37 256mb ddr sdram * eorex reserves the right to change pr oducts or specificat ion without notice. package dimension 11.76 +/- 0.20 0.463 +/- 0.008 pin #1 0 ? 8 ? 0.25 0.010 typ 10.16 0.400 0.50 0.020 0.45 ? 0.75 0.018 ? 0.030 0.125 +0.075 / -0.035 0.005 +0.003 / -0.001 0.05 0.002 min 0.21 +/- 0.05 0.008 +/- 0.002 1.00 +/- 0.10 0.039 +/- 0.004 1.20 0.047 max max 0.10 0.004 0.71 0.028 0.30 +0.08 / -0.08 0.012 +0.003 / -0.003 0.65 0.0256 22.62 0.891 max 22.22 +/- 0.10 0.875 +/- 0.004

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